Protected method for fast writing of data for mass memory apparatus

ABSTRACT

A protected method of fast writing of information for at least one mass memory apparatus (DMM 1 ) belonging to an information processing system including at least one central host (H 1 , H 2 ), two control units (UC 1 , UC 2 ) with independent electrical power supplies (ALIM 1 , ALIM 2 , BAT 1 , BAT 2 ) connected to a first and second parallel bus (B 1 , B 2 ) is disclosed wherein the method is characterized in that, if the host (H 1 , H 2 ) is connected to each of the two buses via at least one first host adaptor (HA 1 , HA 2 ) belonging to the first control unit (UC 1 , UC 2 ) and the mass memory (D 1  -D 5 ) is connected to each of the two buses via a first and a second mass memory adaptor (DA 1 , DA 2 ) belonging to the first and second control unit, respectively, which include a first and a second memory buffer (MTD 1 , MTD 2 ), respectively, 
     I--the block of data to be written is memorized in the first host buffer (MTH 1 , MTH 2 ) and memory buffer (MTD 1 , MTD 2 ); 
     II--the first mass memory adaptor (DA 1 , DA 2 ) reserves the mass memory (D 1  -D 5 , D 6  -D 10 ); 
     III--the mass memory adaptor (DA 1 ) then informs the host adaptor (HA 1 ) of this, which host adaptor then sends an acknowledgement signal to the central host (H 1 ); 
     IV--the operation of writing the block in its entirety is performed in the mass memory under the direction of the first mass memory adaptor (DA 1 ) or the second, if the first is defective. The invention is applicable to mass memory subsystems.

The present invention relates to a protected method of fast writing ofinformation for at least one mass memory apparatus belonging to aninformation processing system including at least one central hostsystem. It is applicable more particularly to writing of information ina set of rotary disk memories.

It is known that an information processing system comprises a centralunit, also called a central host, embodied by at least one centralprocessing unit, and a main memory to which this processor is connected;various peripherals; and an input/output processor that assures controlof the exchange of data between the memory and its various devices.

Peripheral control units or controllers are associated with the variousperipherals and assure the physical transfer of data between the centralhost and the peripherals associated with these various controllers.

Generally, all the functional constituent elements of an informationprocessing system are connected to the same parallel bus, which assuresthe transport of the data among the various boards that these elementshave and also assures the supply of electrical power to them.

One of the most widely used buses of this type at present is theMultibus II (registered trademark of Intel Corporation). Itsarchitecture is structured around a main bus of the parallel type,standardized by the Institute of Electrical and Electronic Engineersunder IEEE standard 1296.

As for the peripherals, mass memories, such as rotary magnetic diskmemories, are especially important. They are very widely used ininformation processing because they enable both the storage of verylarge quantities of information and relatively fast access to it. Theirmean access time is on the order of 20 to 25 ms. The highest-powereddisk memories on the market have capacities that exceed 1 gigabyte.

When the central host wishes for the information to be written in agiven disk memory, the following problem arises: For reasons of cost,volume, and ease of management of the work by this host system, thecentral memory of the host bus has very limited capacity (severalmegabytes) compared with the rotary disk memory. On the other hand, theaccess time to the information contained in the central memory is veryshort, on the order of one or two hundred nanoseconds.

Consequently, when the host system wishes to write information on a diskof a disk memory, it must save the corresponding data in its centralmemory until the recording has been completed in the entire disk inquestion. This has the advantage of assuring the protection of the data;on the other hand, it makes some of the central memory of the hostsystem unavailable for some 20 to 25 ms on average, which isconsiderable, in view of the high speed of current processors, and henceexpensive.

To overcome this disadvantage, an interpolated memory is disposedbetween the host system and the disk memory or memories, as can be seenin FIG. 1a, which schematically shows the version described in FrenchPatent 2.486.291 filed on Jul. 4, 1980. The interpolated memory MI isdisposed between the host system H and a disk memory MD.

The interpolated memory MI includes a first interface circuit I₁ forinterfacing with the host system H; a second interface circuit I₂ forinterfacing with the disk memory MD; a device DC for commanding theinterpolated memory, connected to the two interface circuits I₁ and I₂,on the buffer memory MT, on the other, respectively.

When the host system H seeks to write information into the disk memoryMD, the information passes under the direction of the command device DC,via the first interface circuit I₁ in the command device itself, to thebuffer memory MT, where it is stored. The information waits there to betransferred, under the direction of the command device DC, via theinterface circuit I₂, to the disk memory MD, when the memory locationsin one of the rotary disks of this memory become available. As soon asthe set of information that the host system H seeks to write in the diskmemory MD has been transferred to the buffer memory MT, the host systemcan assign the locations in its central memory that have been madeavailable by the transfer of this information to writing otherinformation. It will be appreciated that from the moment when the dataare transferred to the interpolated memory MI, it is the command deviceDC of that memory that carries out the writing of the applicableinformation in the disk memory MD.

The major disadvantage of the interpolated memory apparatus MI shown inFIG. 1a is as follows: When for any reason such as, for example, adefect of any of the circuits comprising the interpolated memory MI, apower failure for it, maintenance work, etc., the interpolated memory MIfails and the data written in it are lost. This means that the operationof writing the data in the disk memory MD is not performed in completesecurity, i.e., the data is not protected. To overcome thisdisadvantage, in current practice an apparatus inspired by that shown inFIG. 1b, which is equivalent to IBM's mass memory subsystem 3390 isused.

Between the host system H and a set of disk memories D₁ -D₅, thisapparatus includes a high-capacity cache memory MC (several tens ofmegabytes), and a nonvolatile memory MNV associated with an emergencybattery power supply. The cache memory and the nonvolatile memory areconnected to the same internal bus BI that the controller CNT of thedisk memories D₁ -D₅ is also connected to.

When the host system H wishes to write given data into one of the diskmemories D₁ -D₅, the information is first written in the cache memory MCand nonvolatile memory MNV, and the information is then written on thedisk in question by seeking the information in the cache memory.

The major disadvantage of the apparatus shown in FIG. 1b is that a cachememory is used, the unit price of which per megabyte is a dozen timesgreater than the unit price per megabyte of the disks. Moreover, thenonvolatile memory is also very expensive and is therefore not sold onthe market except for high-end equipment.

The present invention makes it possible to overcome these disadvantagesby proposing a method of fast, protected writing of information for amass memory apparatus that is relatively simple and much less expensivethan the methods used in the systems of the prior art.

According to the invention, the method of fast writing of informationfor at least one mass memory apparatus belonging to an informationprocessing system including at least one central host, two control unitsfor independent electrical power supply, respectively having at least afirst and a second central processor and connected to a first and secondparallel bus, is characterized in that, if the host is connected to eachof the two buses via at least one first host adaptor belonging to thefirst control unit and including a first host buffer, and the massmemory is connected to each of the two buses via a first and a secondmass memory adaptor belonging to the first and second control unit, thetwo mass memory adaptors respectively including a first and a secondbuffer associated with the mass memories and known as a memory buffer,the following successive operations are performed:

I--the block of data that the host wishes to write is memorized in thefirst host buffer and then in the first memory buffer by dialog betweenthe host and the host adaptor, on the one hand, and between the hostadaptors and the mass memory adaptors on the other;

II--the first mass memory adaptor requests reservation of the massmemory with a view to writing the aforementioned block there;

III--as soon as the reservation thereof is obtained, the first massmemory adaptor informs the host adaptor of this, and the host adaptorthen sends an acknowledgement signal to the central host;

IV--the operation of writing the block in its entirety is performed inthe mass memory under the direction of the first mass memory adaptor inall cases when it is functioning properly, and by the second mass memoryadaptor when the first is defective.

Thus the method according to the invention uses the buffer memories ofthe host adaptors and mass memory adaptors, buffer memories that arepresent aside from their specific use for the method according to theinvention. They are in any case present in the host adaptors and massmemory adaptors, which are the interface circuits normally used toconnect the central host and the mass memories to buses of the MultibusII type.

Hence the method according to the invention makes it possible to avoidusing specific boards that have to be added, as is the case for examplefor the apparatus of FIG. 1b.

The mass memory apparatus using the method according to the invention isan intelligent subsystem, one that is redundant because it isconstituted by two interconnected controllers, and it alone is capableof proposing a relatively inexpensive fast writing method of this kindthat enables assuring the inscription of data into mass memories incomplete security, i.e., fully protected, regardless of any malfunctionsor accidents that may affect some or all of the apparatus.

Further characteristics and advantages of the present invention willbecome more apparent from the ensuing detailed, non-limiting descriptionand from the accompanying drawings.

In the drawings:

FIG. 1, comprising FIGS. 1a and 1b, shows mass memory apparatus usingwriting methods for mass memories, according to the prior art;

FIG. 2 is a diagram of a first exemplary embodiment of a mass memoryapparatus employing the writing method according to the invention;

FIG. 3 is a diagram showing a second exemplary embodiment of a massmemory apparatus using the writing method according to the invention;

FIG. 4 is a detailed diagram showing the structure of the host adaptorsand mass memory adaptors belonging to the mass memory apparatusaccording to the invention;

FIG. 5, comprising FIGS. 5a and 5b, shows the diagram of the mainconstituent elements of an electronic mass memory and of the centralprocessor belonging to the first and second control unit, respectively,of the mass memory apparatus according to the invention, and FIG. 5bshows how the data are written both inside an electronic mass memory andinside a rotary-disk mass memory;

FIG. 6 shows the flow chart for the dialog between the host adaptor andthe mass memory adaptor that enables the implementation of the writingmethod according to the invention.

DETAILED DESCRIPTION

FIG. 2 will be addressed first. It shows the first exemplary embodimentDMM₁ of the mass memory apparatus implementing the protected fastwriting method according to the invention.

This apparatus DMM₁ can be considered a subsystem of the mass memorybelonging to a much larger information processing system, the centralportion of which for example includes two host systems H₁ and H₂.

Preferably, the apparatus DMM₁ includes two identical control units,that is, UC₁, occupying the left-hand portion of FIG. 2, and UC₂,occupying the right-hand portion.

The architecture of the apparatus DMM₁ is constructed around twoidentical buses that are parallel to one another, preferably of theMultibus II type, designated as B₁ and B₂.

It is seen that the two buses have a central zone where they completelyface one another, and two lateral zones where they do not face oneanother. The two control units UC₁ and UC₂ are strictly identical andsymmetrical to one another with respect to a plane of symmetry PS.

The first control unit UC₁ is supplied with electrical power by a firstpower supply ALIM₁ and is connected to a first emergency electricalpower supply BAT₁, embodied by a battery.

The second control unit UC₂ is also supplied by a second power supplyALIM₂ that is independent of the first and is connected to a secondemergency power supply BAT₂.

The first control unit UC₁ includes the following:

a first central processor PR₁ ;

a first interface board DEI₁ ;

a host adaptor HA₁ including a first buffer memory or host buffer, MTH₁;

a mass memory adaptor DA₁ (disk memories D₁ -D₅), including a firstbuffer memory more commonly known for simplicity as a first memorybuffer MTD₁, this adaptor being called here a disk adaptor for the sakeof simplicity;

the backup disk memory MSD₁.

Similarly, the second control unit UC₂ includes the second centralprocessor PR₂, the second interface board DEI₂, the host adaptor HA₂including the second host buffer MTH₂, the second disk adaptor DA₂including the second memory buffer MTD₂, and the second backup diskmemory MSD₂.

The first and second disk adaptors DA₁ and DA₂ are connected viarespective links CS₁ and CS₃ to a set of disk memories, only five ofwhich are shown in FIG. 2, that is, the disk memories D₁ -D₅. The firstand second disk adaptors DA₁ and DA₂ can also be connected respectivelyvia links CS₂ and CS₄ to a second set of disk memories D₆ -D₁₀, whichare not shown in FIG. 2 for the sake of simplicity.

The links CS₁ -CS₄ are links of the IPI-2 type, standardized by bothANSI (American National Standards Institute) and ISO (InternationalStandards Organization).

The first host adaptor HA₁ is connected to a first host H₁ via a firstlinking channel CE₁, and to a second host H₂ via a second linkingchannel CE₂.

Similarly, the second host adaptor HA₂ is connected to a second host H₂via first linking channel CE₃, and to a first host H₁ via a secondlinking channel CE₄.

The first linking channels CE₁ and CE₃ of the first and second hostadaptors HA₁ and HA₂ have priority over the second linking channels CE₂and CE₄.

The four linking channels CE₁ -CE₄ are of the IPI-3 type standardized byboth ANSI and ISO.

The constituent elements of the first control unit, that is, PR₁, DEI₁,HA₁, DA₁, and MSD₁, are identical and symmetrical to the correspondingelements of the second control unit UC₂, that is, PR₂, DEI₂, HA₂, DA₂,and MSD₂.

The four constituent elements DEI₁, PR₁, PR₂, DEI₂ are connectedsimultaneously to both buses B₁ and B₂, in the central portion of thebuses where the buses face one another.

The constituent elements HA₁ and DA₁ of the first control unit UC₁ areconnected to the first bus B₁, while the corresponding elements HA₂ andDA₂ of the second control unit UC₂ are connected to the second bus B₂.

The first backup disk memory MSD₁ is connected both to the first centralprocessor PR₁ and to the second interface board DEI₂.

Similarly, the second backup disk memory MSD₂ is connected to both thesecond central processor PR₂ and the second interface board DEI₁. Thusboth backup disk memories MSD₁ and MSD₂ are accessible by both the firstand second control unit UC₁ and UC₂ simultaneously.

In FIG. 2 (and in FIG. 3 as well), the mass memory apparatus DMM₁ (orDMM₂ in FIG. 3) is represented as two sets each of five disk memories,but it will be appreciated that the mass memory apparatus may contain alower number, or more often a higher number of disk memories; thisnumber may be as high as several dozen or even a few more than 100.

The second exemplary embodiment of the mass memory apparatus accordingto the invention, DMM₂ shown in FIG. 3, is identical in its broadestoutlines to the first exemplary embodiment DMM₁ shown in FIG. 2, butwith the difference that all of the two buses B₁ and B₂ face oneanother, and that the first and second host adaptors HA₁ and HA₂ areconnected to these two buses simultaneously, while the second massmemory adaptors DA₁ and DA₂ are connected separately, one to the bus B₁and the other to the bus B₂, respectively. The consequences of thisslight difference in structure will become more apparent from theensuing description relating to the functioning of these mass memoryapparatuses according to the invention.

The two central processors PR₁ and PR₂ are figuratively the foremen ofthe various elements belonging to each of the control units UC₁ and UC₂.They load implementation programs of the various elements included inthese control units into them, so that the control units can perform thefunctions assigned to them. The processors PR₁ and PR₂ will look forthese programs, which for example are stored in the backup rotary diskmemories MSD₁ and MSD₂. In that case these latter memories have a dualfunction, that is, first to back up information not yet stored andwaiting to be written in the rotary disk memories D₁ -D₅ (in case of anymalfunction making DA₁ and DA₂ unavailable), and second to store theaforementioned implementation programs. However, these programs could bestored in a special disk memory, or system disk memory, connected toboth the processor PR₁ and the processor PR₂.

Further details of the structure of the host adaptors HA₁, HA₂ and diskadaptors DA₁ and DA₂ can be found in FIG. 4.

The first host adaptor HA₁ includes the following:

an interface IH₁ for linking the two host systems H₁ and H₂ via linkingchannels CE₁ and CE₂, this linking interface being defined by the IPI-2standard;

the host buffer memory, or for simplicity the host buffer MTH₁ ;

the microprocessor MPH₁ ;

the interface IBH₁ for connection with the Multibus II bus B1, thisinterface being defined by the aforementioned standard IEEE 1296, andfor example constituted by a coprocessor of the VL 82c389 type (made byIntel) communicating by message mode with the other constituentfunctional elements of the mass memory apparatus DMM₁ of the invention.

Similarly, the second host adaptor HA₂ includes the interface IH₂ forlinking the two host systems H₁ and H₂ via the two channels CE₃ and CE₄,the second host buffer memory MTH₂, the microprocessor MPH₂, and theinterface IBH₂ for connection with the Multibus II bus B2. It is clearthat the equivalent constituent elements of each of the first and secondhost adaptors HA₁ and HA₂ perform analogous functions.

The respective constituent elements of the first and second hostadaptors communicate with one another via the internal buses BH₁ and BH₂of the microprocessors MPH₁ and MPH₂.

The structure of the first and second disk adaptors DA₁ and DA₂ issimilar to the structure of the host adaptors.

Thus the first adaptor DA₁ includes an interface IBD₁ for connectionwith the bus B₁ defined by IEEE standard 1296 mentioned above; a buffermemory for the disk memories, more simply called a memory buffer, MTD₁ ;the microprocessor MPD₁ ; and finally the interface ID₁ for linking withthe disk memories D₁ -D₅ and D₆ -D₁₀ via the IPI-2-type linking channelsCS₁ and CS₂ (these interfaces are defined by the aforementioned standardIPI-2).

Similarly, the second disk adaptor DA₂ includes the interface IBD₂ forconnection with the bus B₂ defined by the aforementioned IEEE standard1296; the host buffer MTD₂ ; the microprocessor MPD₂ ; and the interfaceID₂ for linking with the two sets of disk memories D₁ -D₅ and D₆ -D₁₀via the linking channels CS₃ and CS₄.

The various constituent elements of the disk adaptors DA₁ and DA₂communicate with one another via the internal buses BD₁ and BD₂ of themicroprocessors MPD₁ and MPD₂.

The broad outlines of the writing method according to the invention,employed by the mass memory apparatus DMM₁ shown in FIGS. 2-4, are asfollows:

I--When the host system H₁, for example, wishes to write a block of datainto any of the disk memories of the set D₁ -D₅, this block of data tobe written is memorized first in the first host buffer MTH₁ and then inthe first memory buffer MTD₁, by successive dialog between the host H₁and the host adaptor HA₁, under the direction, with respect to thelatter, of the microprocessor MPH₁, and also between the host adaptorHA₁ and the disk adaptor DA₁, under the respective direction of themicroprocessors MPH₁ and MPD₁. More precisely, to perform this operationI, the three following suboperations are performed:

1. the host system H₁ sends a request for writing a block of data to thehost adaptor (for example via the channel CE₁);

2. the host adaptor HA₁ requests the host H₁ to transfer the block ofdata to be written;

3. this block is memorized in its entirety first in the host buffer MTH₁and then also in the memory buffer MTD₁ (the block of data to be writtentravel over the internal bus BH₁, the interface IBH₁, the Multibus IIbus B₁, the interface IBD₁ and the internal bus BD₁).

II--The disk adaptor DA₁, under the direction of the microprocessorMPD₁, requests the reservation of the disk memory D₁ -D₅ that isaddressed by the host H₁ (the host in its writing request, indicateswhich disk memory is addressed, that is, the disk memory where the datablock is to be written), with a view to writing the aforementionedblock.

III--As soon as this reservation is obtained by agreement with the diskmemory addressed, the disk adaptor (the microprocessor MPD₁) informs thehost adaptor HA₁ (microprocessor MPH₁) of this, and the latter thensends an acknowledgement signal to the host system H₁. The host systemis then free to perform other operations even though the disk adaptorDA₁ has not yet organized the operation of writing the aforementionedblock of data in the disk memory in question.

IV--The operation of writing the block is performed under the control ofthe microprocessor MPD₁.

The program for dialog between the host adaptor HA₁ and the host systemH₁ is loaded, upon initialization of the mass memory apparatus DMM₁, bythe central processor PR₁ into the microprocessor MPH₁ (or into thememory associated with it, which is not shown in order to simplify FIG.4). Similarly, the program of dialog between the host adaptors and diskadaptors is loaded by the central processor PR₁ into the microprocessorsMPH₁ and MPD₁. The program for writing the block of data into any of thedisk memories D₁ -D₅ (or D₆ -D₁₀) is always loaded, upon initializationof the mass memory apparatus, by the central processor PR₁ into themicroprocessor MPD₁.

It will be understood that what has been described above for the writingmethod according to the invention relating to the first host adaptor andfirst disk adaptor is equally valid for the second host adaptor andsecond disk adaptor, HA₂ and DA₂, respectively.

At the end of operation III, it has been seen that the host, havingreceived an acknowledgement signal from the adaptor HA₁, thinks that theoperation of writing the block of data is performed in the disk memoryaddressed, although in reality this is not true. The mass memoryapparatus DMM₁ then has the responsibility, as soon as this operationIII is completed, of carrying out this operation of writing the block ofdata regardless of any functional accidents that may occur, whether theytake the form of a malfunction of the host adaptors HA₁ or HA₂, diskadaptors DA₁ and DA₂, or the two control units UC₁ and UC₂, eitherseparately or simultaneously, or one or the other of the two buses. Itis specifically an essential object of the writing method according tothe invention to carry out the writing of the data block integrally inthe disk memory addressed in complete security, regardless of theaforementioned circumstances. For this reason, the method according tothe invention is called a protected fast writing method. The variousinstances of malfunction or accidents in the functioning of the massmemory apparatus according to the invention occurring from the end ofoperation III on, with the consequences that this entails for the fastwriting method, are described below.

If the host adaptor HA₁ becomes defective, the disk adaptor DA₁ isunaffected. It always has the data at its disposal in its memory bufferMTD₁ and it performs or completes the writing operation regardless ofthe instant at which HA₁ becomes defective.

If the disk adaptor DA₁ becomes defective, the data block to be writtenis sent by the first host adaptor HA₁ to the second disk adaptor by wayof B₁ and PR₁ (it will be recalled that the first host adaptor HA₁contains the entire data block to be written within its own host bufferMTH₁). The second disk adaptor DA₂ then, instead of the first diskadaptor, performs operations II, III, IV, with the disk adaptor DA₂ indialog with the first central processor PR₁, via the bus B₂, foroperations II and III.

When the mains power supply fails, the two power supplies ALIM₁ andALIM₂ are then inoperative, each control unit UC₁ and UC₂ has its ownprotection battery BAT₁, BAT₂, so that the principle processor PR₁, oncethe loss of mains voltage is detected, organizes the transfer of thedata block contained in the memory buffer MTD₁ to the backup disk memoryMSD₁. It also organizes the transfer of all the necessary instructionsfor effective performance of the operation (the writing program that wascontained in the memory adaptor DA₁) for writing on one of the rotarydisks of the backup disk memory MSD₁. Once the operations of backup tothis latter memory are completed, the main processor PR₁ requestsdisconnection of the battery BAT₁. It will be understood that operationsanalogous to these performed by the processor PR₁ are performed by theprocessor PR₂.

Once the mains power supply is back in operation, the main processor PR₁detects this and returns the control unit UC₁ to the state in which itwas immediately prior to the outage, by looking for the necessaryinformation that has been backed up in the backup disk memory MSD₁. Thusthe block of data to be written is re-sent to the memory buffer MTD₁,the writing program having been re-inscribed in the microprocessor MPD₁.The first processor communicates this resumption of the state prior tothe power outage to the central host, and it can resume the operationsII, III, IV mentioned above. It should be noted that the data block tobe written is rewritten in its entirety in the disk memory in the regionreserved for this purpose (specified by H₁ in its writing request), evenif part of this block had been written there before the mains poweroutage.

In the event of a malfunction of the main processor PR₁, it is certainlypossible to gain access to the backup disk memory MSD₁ from the othercontrol unit, via the interface board DEI₂, both for backup operationsand for operations of context reinitialization, and in the event of apower outage the operations are then performed under the control of thesecond main processor PR₂.

Similarly, if PR₁ is defective, any writing operation performed by thehost adaptor and disk adaptor HA₁ and DA₁ is performed in associationwith the main processor PR₂.

If the Multibus II B₁ breaks down, the disk adaptor DA₁, still retainingthe block to be written in its memory (in MTD₁), performs its writingtask normally.

The structure of the memory apparatus DMM₂ according to the inventionshown in FIG. 3 makes it possible not only to take care of theaforementioned functional accidents (in the host adaptor, memoryadaptor, main processor, or power outage of the two control units ormalfunction of the bus B₁ and/or B₂) but also to take care of thefollowing accident, that is, a malfunction of one or the other of thecontrol units while the writing method according to the invention is inprogress, assuming that the information has been memorized in the hostbuffers and memory buffers.

Thus as can be seen in FIG. 3, as soon as the data block to be writtenhas been inscribed in the host buffer MTH₁, this same block of data tobe written is transmitted to the disk adaptor DA₂, where it is inscribedin the memory buffer MTD₂, the information traveling from the first hostadaptor HA₁ to the second disk adaptor DA₂ by way of the bus B₂, whetheror not UC₁ is functional. Thus, the data block having been transferredto the memory buffer of the disk adaptor DA₂, this disk adaptor nowcarries out the writing operation in association with the main processorPR₂ and the host adaptor HA₁, whether UC₁ is functional or defective.

FIG. 6 will now be described, which illustrates the dialog between thehost adaptor HA₁ and the disk adaptor DA₁, when a block of data is to bewritten into one of the disk memories D₁ -D₅ (D₆ -D₁₀).

This dialog includes the following eight steps:

1) Step E1: The host adaptor receives the writing request from the hostin the form of a command message CMD, which is sent in a stack ofcommands for instance located in the read-write memory of themicroprocessor MPH₁. Within this command message, the microprocessordecodes the address of the disk memory in which the data block is to bewritten. This disk memory will be called the resource, for the sake ofsimplicity. As soon as the microprocessor MBH₁ has decoded the addressof the resource, it constitutes a command message MSG, which is sent tothe microprocessor of the disk adaptor DA₁. The next step follows.

2) Step E2: This command message, MSG CMD, is decoded by themicroprocessor MPD₁, which verifies the validity of the message andrequests reservation of the resource from the main processor PR₁. Itthen assigns one page (or more) of the memory buffer MTD₁ for laterreceiving the data block.

As soon as the main processor PR₁ notifies the disk adaptor of thereservation of the aforementioned resource, the microprocessor MPD₁ thensends a message to the host adaptor HA₁ requesting that this adaptorsend it the information, that is, the block of data to be written. Thenext step follows.

3) Step E3: The microprocessor MPH then assigns a page of the hostbuffer MTH₁ and notifies the host H₁ that it is waiting for the transferof the data block to the page of the aforementioned host buffer. It thensends a request for reservation of the memory buffer MTD₁ to the diskadaptor DA₁, which returns a message to the host adaptor indicating thatthe memory buffer MTD₁ has agreed. The next step follows.

4) Step E4: The host adaptor transmits the block of data to be writtento the memory buffer of the disk adaptor, but the block of data to bewritten is still memorized in any case in the host buffer. Once thistransfer is completed, the next operation follows.

5) Operation E5: The microprocessor MPD₁ constitutes a response messagesignifying that the transfer of the entire data block to be written hastaken place normally. This response message is transmitted to themicroprocessor MPH₁ of the host adaptor. Upon reception of this messagethe next operation follows.

6) Operation E6: The microprocessor MPH₁ then sends a message to thehost system H₁ indicating that the transfer of the block of data to bewritten in the host buffer and memory buffer has taken place. The hostthen considers that the data block to be written has been written in theresource in question, even though this writing has not yet actuallytaken place.

For the host system H₁, it is seen that the access time to the reserveddisk memory is thus masked, and it can re-use the zone in its centralmemory that it had expressly reserved for the data block to be written.The next operation follows.

7) Operation E7: Under the direction of the microprocessor MPD₁, thedata block is written in one of the rotary disks of the resource inquestion. To do this, the writing program employed by thismicroprocessor cuts the data block to be written into sectors, all ofwhich have the same length, which is currently usual in fixed-formatdisk memories, as indicated in FIG. 5b. The data are divided intosectors S_(i), S_(j), S_(k), containing the same number of bytes (512,for example). In each sector S_(j), a header HE_(j), a data block DO_(j)and a footer IC_(j) are written successively into each sector S_(j). Theset of information of one sector is inscribed over all or some of one ormore tracks (if the data block to be written is sufficiently long) ofone of the rotary disks of the resource. The preamble containsinformation for physically locating the sector S_(j) on the track inquestion of the magnetic disk, and the footer contains information forverifying the integrity of the data, to verify whether all the bytes ofthe sector S_(j) that have been recorded are correct. This organizationof writing information by sector, and its distribution among thesectors, is very well known and is currently used in conventional diskmemories. Once writing of the data block in the disk of the resource inquestion is completed, this resource is released by the microprocessorMPD₁, as is the memory buffer MTD₁. The microprocessor in question thensends a release message to the adaptor HA₁. The final step follows.

8) Step E8: The microprocessor MPH₁ releases its host buffer MTH₁.

FIG. 5a will now be described.

In a particularly preferred embodiment of the invention, each of theinterfaces DEI₁ and DEI₂ comprises an electronic memory, which iscurrently known as such, or as an electronic disk, to those skilled inthe art.

The electronic disk DEI₁ includes a set of commands EC₁ and a memoryplane PM.

The set of commands EC_(I) is connected via a link L₁ to the backup diskmemory MSD₁, which is connected by a link L₂ to the main processor PR₂.

The set of commands EC_(I) includes in particular an interface IB₁ forcommunication with the bus B₁, an interface IB₂ for communication withthe bus B₂, a command microprocessor MPE, and the memory M₁ associatedwith this microprocessor, as well as an interface IF₁ with the link L₁.These various elements exchange information by way of the internal busBI₁ of the set of commands EC₁.

The memory plane PM is composed for example of two memory planes P₁ andP₂. The memory plane P₁ includes a plurality of RAM memory columns, forexample, specifically the columns IR₁, IR_(j), . . . , IR_(n).Similarly, the memory plane P₂ includes a plurality of semiconductor RAMmemory columns, that is, 2R₁, . . . 2R_(j), . . . , 2R_(n).

The information (data and addresses where the data are located insidethe RAM memories) originating from or proceeding to the memory plane P₁is transported on a bus BDA₁, while the information circulating betweenthe two memory planes P₁ and P₂ is carried by a bus BDA₂ that isidentical to the bus BDA₁. Each of these two buses is in fact composedof one data bus and one address bus. Inside the memory planes P₁ and P₂,each of the two buses BDA₁ and BDA₂ is subdivided into a sufficientnumber of branches to supply all the columns of each of these twoplanes.

The central processor PR₂ (the central processor PR₁ has an entirelyidentical structure) includes two interfaces for communication with thebuses B₁ and B₂ respectively, that is, interfaces IB₃ and IB₄ ; acommunication bus BI₂ ; a central microprocessor MPC; the memory M₂associated with this microprocessor; and finally, an interface IF₂ withthe link L₂.

The interfaces IB₁, IB₂, IB₃, IB₄ are of the same type as the interfacesIBH₁, IBH₂, IBD₁, IBD₂ (see above). The interfaces IF₁ and IF₂ arestandardized IPI-2 interfaces. If it is desired to write information inthe electronic disk DEI₁, the information travels over one of the twobuses B₁ or B₂, passes via the interface IB₁ (IB₂) and is thentransmitted to the memory M₁ associated with the microprocessor MPE. Asa function of the available regions in one or the other of the memoryplanes P₁ and P₂, this microprocessor inscribes the information intothem. Further details of the functioning of the electronic disk unitDEI₁ are given in French Patent Application No. 89.15914, filed on Dec.1, 1989 by the present assignee and corresponding to U.S. applicationSer. No. 07/620,471 of Daniel Carteau for "Protected Electronic MassMemory Unit" filed Nov. 30, 1990, the subject matter of which is herebyincorporated by reference.

The fast writing method according to the invention is equally applicableto the electronic memory DEI₁. In the same way as in rotary diskmemories, the data block to be written is divided into sectors S_(i),S_(j), S_(k), containing the same number of bytes, and the set ofinformation of one sector is inscribed at memory locations the addressesof which are in sequence, for example in one unit. In a preferredembodiment of the invention, the data are written in a 39-bit format,that is, 32 useful bits distributed among four bytes, with seven errorcorrection bits ECC added; this error correction mode is conventionallyused in dynamic RAMs.

To use the fast writing method of the invention in an electronic disksuch as DEI₁, it is sufficient to substitute the set of commands EC₁ forthe disk adaptor DA₁ in the entire above explanation; the microprocessorMPE then plays the same role as the microprocessor MPD₁ and the memoryplane pM plays the same role as the host buffer MTD₁ of the hostadaptor. Once the data have been written in the memory plane (and havethus also been written in the host buffer MTH₁), the backup disk memoryMSD₁ is updated, in masked time (it can be seen that in the fast writingmethod, this backup disk memory plays the same role that the resourceplayed in the above description of the fast writing method applied todisk memories).

It can be seen that the fast writing and data protection method isaccordingly identically applicable to either conventional disk memoriessuch as D₁ -D₅ or electronic disks such as DE₁ or DE₂.

The mass memory apparatus according to the invention accordinglyproposes a fast writing method that assures complete protection of thedata, since the data inscribed there are perfectly well protected fromvarious functional accidents (see above) that may occur.

We claim:
 1. A method of fast writing of information for at least onemass memory apparatus (DMM₁) including a plurality of mass memory unitsand belonging to an information processing system including at least onecentral host (H₁, H₂), a first and second control unit (UC₁, UC₂),connected to a first and second parallel bus (B₁, B₂), wherein saidcontrol units (UC1, UC2) include a first and second central processor(PR₁ and PR₂), respectively, the central host (H₁, H₂) being connectedto each of the buses via at least one first host adaptor (HA₁, HA₂) ofthe first control unit (UC₁, UC₂), and at least a first and second massmemory device for controlling and organizing writing of information oneach mass memory unit, said mass memory device being connected to atleast one of said first and second parallel buses, wherein said at leastone host adaptor, the mass memory device and the mass memory units areon the same data path; comprising the steps ofI) storing a block of datato be written, sent from the central host, in the first host adaptor(HA₁, HA₂) and then in the first mass memory device (DA₁, DA₂) bycommunication between the central host (H₁, H₂) and the host adaptors(HA₁, HA₂), and between the host adaptors and the mass memory device(DA₁, DA₂), respectively; II) causing the first mass memory device (DA₁,DA₂) to send a request to the first central processor for reservation ofthe mass memory (D₁ -D₅) for writing information therein; III) informingthe host adaptor (HA₁), by signal from the mass memory device, that thereservation request has been made, and sending an acknowledgement signalfrom the host adaptor HA₁ to the central host (H₁); and IV) writing theblock of data in its entirety in the mass memory under the control ofthe first mass memory device (DA₁), in all cases when the first massmemory adapter is functioning properly, and by the second mass memorydevice (DA₂) when the first mass memory device (DA₁) is defective,wherein if said first mass memory device is defective the block of datais transferred to said second mass memory device.
 2. The method of claim1, wherein the first step I includes the following successive steps:1)sending a writing request from the host H₁ to the first host adaptor(HA₁); 2) sending a transfer request from the host adaptor (HA₁) to thehost to transfer the block of data to be written; 3) storing the blockof data in its entirety, first in a first host buffer (MTH₁) within thefirst host adaptor (HA₁, HA₂), and then also in a first memory buffer(MTD₁) within the first memory device (DA₁, DA₂).
 3. The method of claim1, wherein when the first mass memory adaptor (DA₁) is defective afterstep III, said method includes the steps of:a) sending the block of databy the host adaptor (HA₁) to the second mass memory device (DA₂); and b)causing the second mass memory device (DA₂) to control the performanceof steps II, III, IV, instead of having the steps controlled by thefirst memory device (DA₁).
 4. The method of claim 1, wherein the firstcontrol unit (UC₁) includes at least one first backup rotary disk memory(MDS₁) connected both to the first central processor (PR₁) of said firstcontrol unit and to an interface board (DEI₂) of the second control unit(UC₂) for interfacing with the first and second buses (B₁, B₂), and saidsecond control unit further includes at least one second backup rotarydisk memory (MSD₂) connected both to the second central processor (PR₂)of the second control unit and to an interface board (DEI₁) of the firstcontrol unit for interfacing with the first and second buses connectedto the first control unit, independent power supplies for said first andsecond control units, each control unit having its own protectionbattery, such that if the power supplies are out or defective duringstep IV, the following steps are performed:V) causing the first centralprocessor (PR₁) to extract the data block to be written, contained inthe first memory buffer (MTD₁), and transferring the extracted dataintegrally to the backup disk memory (MSD₁); VI) then causing the firstcentral processor to disconnect the protection battery (BAT₁).
 5. Themethod of claim 1, characterized in that if one or the other of the twobuses is defective, during step IV, continuing step IV, under thedirection of the first mass memory device (DA₁).
 6. The method of claim1, characterized in that when the first host adaptor is connected toboth of the two buses (B₁, B₂), and the first and second memory devices(DA₁ ; DA₂) are connected, one to the first bus (B₁), and the other tothe second bus (B₂), respectively, the second mass memory deviceperforms steps I-IV, V-IX, instead of the first mass memory device. 7.The method of claim 2, characterized in that if one or the other of thetwo buses is defective, during step IV, continuing step IV, under thedirection of the first mass memory device (DA₁).
 8. The method of claim2, characterized in that when the first host adaptor is connected toboth of the two buses (B₁, B₂), and the first and second memory devices(DA₁ ; DA₂) are connected, one to the first bus (B₁), and the other tothe second bus (B₂), respectively, the second mass memory deviceperforms step I-IV, V-IX, instead of the first mass memory device. 9.The method of claim 2, wherein when the first mass memory device (DA₁)is defective after steps III, said method includes the steps of:a)sending the block of data by the host adaptor (HA₁) to the second massmemory device (DA₂); and b) causing the second mass memory device (DA₂)to control the performance of steps II, III, IV, instead of having thesteps controlled by the first memory device (DA₁).
 10. The method ofclaim 2, wherein the first control unit (UC₁) includes at least onefirst backup rotary disk memory (MDS₁) connected both to the firstcentral processor (PR₁) of said first control unit and to an interfaceboard (DEI₂) of the second control unit (UC₂) for interfacing with thefirst and second buses (B₁, B₂), and said second control unit furtherincludes at least one second backup rotary disk memory (MSD₂) connectedboth to the second central processor (PR₂) of the second control unitand to an interface board (DEI₁) of the first control unit forinterfacing with the first and second buses connected to the firstcontrol unit, independent power supplies for said first and secondcontrol units, each control unit having its own protection battery, suchthat if the power supplies are out or defective during step IV, thefollowing steps are performed:V) causing the first central processor(PR₁) to extract the data block to be written, contained in the firstmemory buffer (MTD₁), and transferring the extracted data integrally tothe backup disk memory (MSD₁); VI) then causing the first centralprocessor to disconnect the protection battery (BAT₁).
 11. The method ofclaim 10, characterized in that when the first host adaptor is connectedto both of the two buses (B₁, B₂), and the first and second memorydevices (DA₁ ; DA₂), are connected, one to the first bus (B₁), and theother to the second bus (B₂), respectively, the second mass memorydevice performs step I-IV, V-IX, instead of the first mass memorydevice.
 12. The method of claim 10, characterized in that as soon as thepower supplies are restored to normal operation, the following steps areperformedVII) initializing the first and second control units (UC₁,UC₂); VIII) informing the central host (H₁) from the first processor ofreinitiating of the first and second control units and transferring thedata contained in the backup disk memory (MSD₁) to a first host buffer(MTH₁) and to a first memory buffer (MTD₁); and IX) repeating step II,III and IV.
 13. The method of claim 10, wherein if the first processor(PR₁) is defective, repeating steps V and VI by the second processor(PR₂), and vice versa.
 14. The method of claim 12, characterized in thatwhen the first host adaptor is connected to both of the two buses (B₁,B₂), and the first and second memory devices (DA₁ ; D₂) are connected,one to the first bus (B₁), and the other to the second bus (B₂),respectively, the second mass memory device performs step I-IV, V-IX,instead of the first mass memory device.
 15. The method of claim 12,wherein if the first processor (PR₁) is defective, repeating the stepsVII, VIII, IX by the second processor (PR₂), and vice versa.
 16. Themethod of claim 3, wherein the first control unit (UC₁) includes atleast one first backup rotary disk memory (MSD₁) connected both to thefirst central processor (PR₁) of said first control unit and to aninterface board (DEI₂) of the second control unit (UC₂) for interfacingwith the first and second buses (B₁, B2), and said second control unitfurther includes at least one second backup rotary disk memory (MSD₂)connected both to the second central processor (PR₂) of the secondcontrol unit and to an interface board (DEI₁) of the first control unitfor interfacing with the first and second buses connected to the firstcontrol unit, independent power supplies for said first and secondcontrol units, each control unit having its own protection battery, suchthat if the power supplies are out or defective during step IV, thefollowing steps are performed:V) causing the first processor (PR₁) toextract the data block to be written, contained in the first memorybuffer (MTD₁), and transferring the extracted data integrally to thebackup disk memory (MSD₁); VI) then causing the first central processorto disconnect the protection battery (BAT₁).
 17. The method of claim 16,wherein if the first processor (PR₁) is defective, repeating steps V andVI by the second processor (PR₂), and vice versa.
 18. The method ofclaim 16, characterized in that as soon as the power supplies arerestored to normal operation, the following steps are performedVI)initializing the first and second control units (UC₁, UC₂); VIII)informing the central host (H₁) from the first processor of reinitiatingof the first and second control units and transferring the datacontained in the backup disk memory (MSD₁) to a first host buffer (MTH₁)and to a first memory buffer (MTD₁); and IX) repeating steps II, III andIV.
 19. The method of claim 16, characterized in that when the firsthost adaptor is connected to both of the two buses (B₁, B₂), and thefirst and second memory devices (DA₁ ; DA₂) are connected, one to thefirst bus (B₁), and the other to the second bus (B₂), respectively, thesecond mass memory device performs step I-IV, V-IX, instead of the firstmass memory device.
 20. The method of claim 18, wherein if the firstprocessor (PR₁) is defective, repeating steps VII, VIII, IX by thesecond processor (PR₂), and vice versa.
 21. The method of claim 18,characterized in that when the first host adaptor is connected to bothof the two buses (B₁, B₂), and the first and second memory devices (DA₁; D₂) are connected, one to the first bus (B₁), and the other to thesecond bus (B₂), respectively, the second mass memory device performssteps I-IV, V-IX, instead of the first mass memory device.
 22. Themethod of claim 4, wherein if the first processor (PR₁) is defective,repeating steps V and VI by the second processor (PR₂), and vice versa.23. The method of claim 4, characterized in that as soon as the powersupplies are restored to normal operation, the following steps areperformedVII) initializing the first and second control units (UC₁,UC₂); VIII) informing the central host (H₁) from the first processor ofreinitiating of the first and second control units and transferring thedata contained in the backup disk memory (MSD₁) to a first host buffer(MTH₁) and to a first memory buffer (MTD₁); and IX) repeating steps II,III and IV.
 24. The method of claim 4, characterized in that when thefirst host adaptor is connected to both of the two buses (B₁, B₂), andthe first and second memory devices (DA₁ ; DA₂) are connected, one tothe first bus (B₁), and the other to the second bus (B₂), respectively,the second mass memory device performs steps I-IV, V-IX, instead of thefirst mass memory device.
 25. The method of claim 23, wherein if thefirst processor (PR₁) is defective, repeating steps V and VI by thesecond processor (PR₂), and vice versa.
 26. The method of claim 23,characterized in that when the first host adaptor is connected to bothof the two buses (B₁, B₂), and the first and second memory devices (DA₁; DA₂) are connected, one to the first bus (B₁), and the other to thesecond bus (B₂), respectively, the second mass memory device performssteps I-IV, V-IX, instead of the first mass memory device.